1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory and a fabrication method for the same. More specifically, it relates to a nonvolatile semiconductor memory used for a flash memory and a fabrication method for the same.
2. Description of the Related Art
An electronically erasable programmable read-only memory (EEPROM), for example, is well-known as a conventional nonvolatile semiconductor memory. In an EEPROM, particularly in the case of a NAND type, memory cells are deployed at respective intersections where word lines extending in a row and bit lines extending in a column cross each other, constituting a memory cell array. A MOS transistor having a stacked gate structure made up of a stacked floating gate electrode and a control gate electrode is typically used as the memory cell.
NAND flash memory is structured to include multiple memory cell transistors, which are connected in series to form a NAND string, and select transistors deployed on the respective sides of that NAND string. In addition, element isolation regions are arranged parallel to active regions of the memory cells, constituting a memory cell array. The gate length of the select transistors is typically longer than that of the memory cell transistors. This structure impairs cutoff characteristics of the transistors due to a short channel effect. Furthermore, the select transistors are typically constituted by enhancement mode MOS transistors.
A nonvolatile semiconductor memory, which uses memory transistors and memory cells made up of two select transistors and which is structured with the memory cell transistors and the select transistors differing in gate insulating film thickness has been disclosed (see Japanese Patent Application Laid-open No. 2000-269361).
In addition, a structure where a gate insulating film of a selection MOS transistor formed of a gate electrode and that of a MOS transistor of a peripheral circuit, respectively differing in thickness, has also been disclosed (see Japanese Patent Application Laid-open No. Hei 04-165670).
Furthermore, a nonvolatile semiconductor memory including low resistance peripheral transistors and reduced cell size areas, in which a metal silicide layer is formed on the diffusion layers of the memory cell transistors and the peripheral transistors, and in which the gate electrodes of the peripheral transistors and the memory cell transistors have a self-aligned contact structure, has been proposed (see Japanese Patent Application Laid-open No. 2002-217319).
A conventional nonvolatile semiconductor memory, such as flash EEPROM, requires a high-voltage circuit region for supplying high-voltage pulses such as a write-in voltage, an intermediate voltage, or an erase voltage to a cell array region. A low-voltage circuit region requiring normal low-voltage and high-speed performance is also needed.
In the low-voltage circuit region, it is preferable to use transistors having improved transistor drive capability and higher-speed performance due to that capability. Particularly, providing transistor driving capability in the low-voltage circuit region of the flash EEPROM, capable of low power supply voltage operation, is an objective to be attained.